Design of a VLSI Decoder for Partially Structured LDPC Codes

Table 4

Memory occupation breakdown.

Split decoding
Memory	Instances	Parallelism	Words	⌈Words⌉	Area	Total area
DMEM	85	8	⌈2𝐸+𝑚+𝑛𝑃⌉	256	12000𝜇m^2	1.0mm^2
CMEM	1	7⋅𝑃=595	𝐷sd/2	512	750⋅10^3𝜇m^2	0.75mm^2
LLR MEM	85	8	⌈𝑛𝑃⌉	32	2550𝜇m^2	0.22mm^2
ACC MEM	85	8	𝑛max(⌈𝑃𝑚⌉,⌈𝑃⌉)	32	2550𝜇m^2	0.22mm^2
S/R MEM	85	8	𝑛max(⌈𝑃𝑚⌉,⌈𝑃⌉)	32	2550𝜇m^2	0.22mm^2
					Total	2.36 mm^2
Partition and scheduling (collision)
Memory	Instances	Parallelism	Words	⌈Words⌉	Area	Total area
DMEM	85	8	𝐸⌈2𝑃⌉	256	12000𝜇m^2	1.0mm^2
CMEM	1	7⋅𝑃=595	𝐷coll/2	2048	2.8⋅10^6𝜇m^2	2.8mm^2
LLR MEM	85	8	⌈𝑛𝑃⌉	32	2550𝜇m^2	0.22mm^2
ACC MEM	85	8	𝑛max(⌈𝑃𝑚⌉,⌈𝑃⌉)	32	2550𝜇m^2	0.22mm^2
					Total	4.24 mm^2