Table of Contents Author Guidelines Submit a Manuscript
International Journal of Digital Multimedia Broadcasting
Volume 2009 (2009), Article ID 503130, 13 pages
http://dx.doi.org/10.1155/2009/503130
Research Article

3G Long Term Evolution Baseband Processing with Application-Specific Processors

1Department of Computer Systems, Tampere University of Technology, P.O. Box 553, 33101 Tampere, Finland
2Centre for Wireless Communications, University of Oulu, P.O. Box 4500, 90014 Oulu, Finland
3Information Processing Laboratory, Department of Electrical and Information Engineering, University of Oulu, P.O. Box 4500, 90014 Oulu, Finland

Received 13 November 2008; Accepted 6 January 2009

Academic Editor: Daniel Iancu

Copyright © 2009 Perttu Salmela et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. R. Bachl, P. Gunreben, S. Das, and S. Tatesh, “The long term evolution towards a new 3GPP air interface standard,” Bell Labs Technical Journal, vol. 11, no. 4, pp. 25–51, 2007. View at Publisher · View at Google Scholar
  2. R. W. Chang and R. A. Gibby, “A theoretical study of performance of an orthogonal multiplexing data transmission scheme,” IEEE Transactions on Communication Technology, vol. 6, no. 4, pp. 529–540, 1968. View at Publisher · View at Google Scholar
  3. G. J. Foschini and M. J. Gans, “On limits of wireless communications in a fading environment when using multiple antennas,” Wireless Personal Communications, vol. 6, no. 3, pp. 311–335, 1998. View at Publisher · View at Google Scholar
  4. C. Berrou, A. Glavieux, and P Thitimajshima, “Near Shannon limit error-correcting coding and encoding: turbo-codes. 1,” in Proceedings of IEEE International Conference on Communications (ICC '93), vol. 2, pp. 1064–1070, Geneva, Switzerland, May 1993. View at Publisher · View at Google Scholar
  5. A. J. Paulraj, D. A. Gore, R. U. Nabar, and H. Bölcskei, “An overview of MIMO communications—a key to gigabit wireless,” Proceedings of the IEEE, vol. 92, no. 2, pp. 198–218, 2004. View at Publisher · View at Google Scholar
  6. K. Higuchi, H. Kawai, N. Maeda, H. Taoka, and M. Sawahashi, “Experiments on real-time 1-Gb/s packet transmission using MLD-based signal detection in MIMO-OFDM broadband radio access,” IEEE Journal on Selected Areas in Communications, vol. 24, no. 6, pp. 1141–1153, 2006. View at Publisher · View at Google Scholar
  7. M. Woh, S. Seo, H. Lee et al., “The next generation challenge for software defined radio,” in Proceedings of the 7th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS '07), vol. 4599 of Lecture Notes in Computer Science, pp. 343–354, Springer, Samos, Greece, July 2007. View at Publisher · View at Google Scholar
  8. D. Perels, S. Haene, P. Luethi et al., “ASIC implementation of a MIMO-OFDM transceiver for 192?Mbps WLANs,” in Proceedings of the 31st European Solid-State Circuits Conference (ESSCIRC '05), pp. 215–218, Grenoble, France, September 2005. View at Publisher · View at Google Scholar
  9. B. Cerato, G. Masera, and E. Viterbo, “Enabling VLSI processing blocks for MIMO-OFDM communications,” VLSI Design, vol. 2008, Article ID 351962, 10 pages, 2008. View at Publisher · View at Google Scholar
  10. “TMS320C64x Technical Overview,” Texas Instruments, SPRU395B, January 2001.
  11. “TMS320C64x DSP Library Programmer's reference,” Texas Instruments, SPRU565B, October 2003.
  12. Y.-T. Lin, P.-Y. Tsai, and T.-D. Chiueh, “Low-power variable-length fast Fourier transform processor,” IEE Proceedings: Computers and Digital Techniques, vol. 152, no. 4, pp. 499–506, 2005. View at Publisher · View at Google Scholar
  13. S. Y. Lim and A. Crosland, “Implementing FFT in a FPGA coprocessor,” in Proceedings of the International Embedded Solution Event, pp. 230–233, Santa Clara, Calif, USA, September 2004.
  14. T. Pitkänen, R. Mäkinen, J. Heikkinen, T. Partanen, and J. Takala, “Low-power, high-performance TTA processor for 1024-point fast fourier transform,” in Proceedings of the 6th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS '06), vol. 4017 of Lecture Notes in Computer Science, pp. 227–236, Springer, Samos, Greece, July 2006. View at Publisher · View at Google Scholar
  15. S. Y. Kung, VLSI Array Processors, Prentice-Hall, Upper Saddle River, NJ, USA, 1987.
  16. A. Maltsev, V. Pestretsov, R. Maslennikov, and A. Khoryaev, “Triangular systolic array with reduced latency for QR-decomposition of complex matrices,” in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS '06), pp. 385–388, Kos, Greece, May 2006. View at Publisher · View at Google Scholar
  17. C. K. Singh, S. H. Prasad, and P. T. Balsara, “VLSI architecture for matrix inversion using modified gram-schmidt based QR decomposition,” in Proceedings of the 20th International Conference on VLSI Design jointly with the 6th International Conference on Embedded Systems (VLSID '07), pp. 836–841, Bangalore, India, January 2007. View at Publisher · View at Google Scholar
  18. Altera Corporation, “Implementation of CORDIC-based QRD-RLS algorithm on Altera Stratix FPGA with embedded Nios soft processor technology,” White Paper WP-STXQRD-01, Altera Corporation, San Jose, Calif, USA, March 2004. View at Google Scholar
  19. F. Edman and V. Öwall, “A scalable pipelined complex valued matrix inversion architecture,” in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS '05), vol. 5, pp. 4489–4492, Kobe, Japan, May 2005. View at Publisher · View at Google Scholar
  20. P. Salmela, A. Burian, H. Sorokin, and J. Takala, “Complex-valued QR decomposition implementation for MIMO receivers,” in Proceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '08), pp. 1433–1436, Las Vegas, Nev, USA, March-April 2008. View at Publisher · View at Google Scholar
  21. M. Myllylä, J.-M. Hintikka, J. R. Cavallaro, M. Juntti, M. Limingoja, and A. Byman, “Complexity analysis of MMSE detector architectures for MIMO OFDM systems,” in Proceedings of the 39th Asilomar Conference on Signals, Systems and Computers, pp. 75–81, Pacific Grove, Calif, USA, October-November 2005. View at Publisher · View at Google Scholar
  22. Z. Guo and P. Nilsson, “Algorithm and implementation of the K-best sphere decoding for MIMO detection,” IEEE Journal on Selected Areas in Communications, vol. 24, no. 3, pp. 491–503, 2006. View at Publisher · View at Google Scholar
  23. M. Wenk, M. Zellweger, A. Burg, N. Felber, and W. Fichtner, “K-best MIMO detection VLSI architectures achieving up to 424 Mbps,” in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS '06), pp. 1151–1154, Kos, Greece, May 2006. View at Publisher · View at Google Scholar
  24. K.-W. Wong, C.-Y. Tsui, R. S.-K. Cheng, and W.-H. Mow, “A VLSI architecture of a K-best lattice decoding algorithm for MIMO channels,” in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS '02), vol. 3, pp. 273–276, Phoenix, Ariz, USA, May 2002. View at Publisher · View at Google Scholar
  25. J. Antikainen, P. Salmela, O. Silvén, M. Juntti, J. Takala, and M. Myllyä, “Fine-grained application-specific instruction set processor design for the K-best list sphere detector algorithm,” in Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS '08), pp. 108–115, Samos, Greece, July 2008. View at Publisher · View at Google Scholar
  26. S. Agarwala, T. Anderson, A. Hill et al., “A 600-MHz VLIW DSP,” IEEE Journal of Solid-State Circuits, vol. 37, no. 11, pp. 1532–1544, 2002. View at Publisher · View at Google Scholar
  27. Xilinx, “3GPP Turbo Decoder v3.1,” DS318, May 2007.
  28. T. Vogt and N. Wehn, “A reconfigurable application specific instruction set processor for viterbi and log-MAP decoding,” in Proceedings of IEEE Workshop on Signal Processing Systems Design and Implementation (SIPS '06), pp. 142–147, Banff, Canada, October 2006. View at Publisher · View at Google Scholar
  29. P. Salmela, H. Sorokin, and J. Takala, “A programmable max-log-MAP turbo decoder implementation,” VLSI Design, vol. 2008, Article ID 319095, 17 pages, 2008. View at Publisher · View at Google Scholar
  30. H. Corporaal, “Design of transport triggered architectures,” in Proceedings of the 4th IEEE Great Lakes Symposium on VLSI (GLSV '94), pp. 130–135, Notre Dame, Ind, USA, March 1994. View at Publisher · View at Google Scholar
  31. I. Karkowski and H. Corporaal, “A framework for design of heterogeneous multi-processor embedded systems,” Tech. Rep. 1-68340-44/1997/12, Delft University of Technology, Delft, The Netherlands, 1997. View at Google Scholar
  32. J. Guo, K. Dai, and Z. Wang, “A heterogeneous multi-core processor architecture for high performance computing,” in Proceedings of the 11th Asia-Pacific Conference on Advances in Computer Systems Architecture (ACSAC '06), vol. 4186 of Lecture Notes in Computer Science, pp. 359–365, Springer, Shanghai, China, September 2006. View at Publisher · View at Google Scholar
  33. T. Ahonen and J. Nurmi, “Integration of a NOC-based multimedia processing platform,” in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL '05), pp. 606–611, Tampere, Finland, August 2005. View at Publisher · View at Google Scholar
  34. G. Tempesti, P.-A. Mudry, and R. Hoffmann, “A move processor for bio-inspired systems,” in Proceedings of NASA/DoD Conference on Evolvable Hardware (EH '05), pp. 262–271, Washington, DC, USA, June-July 2005. View at Publisher · View at Google Scholar
  35. J. Rossier, Y. Thoma, P.-A. Mudry, and G. Tempesti, “MOVE processors that self-replicate and differentiate,” in Proceedings of the 2nd International Workshop on Biologically Inspired Approaches to Advanced Information Technology (BioADIT '06), vol. 3853 of Lecture Notes in Computer Science, pp. 160–175, Springer, Osaka, Japan, January 2006. View at Publisher · View at Google Scholar
  36. M. Myllylä, P. Silvola, M. Juntti, and J. R. Cavallaro, “Comparison of two novel list sphere detector algorithms for MIMO-OFDM systems,” in Proceedings of the 17th IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC '06), pp. 1–5, Helsinki, Finland, September 2006. View at Publisher · View at Google Scholar
  37. 3GPP, “Multiplexing and channel coding (release 8),” Technical Specification TS.36.212 v1.0.0, Group Radio Access Network, 3rd Generation Partnership Project, Cedex, France, 2007. View at Google Scholar
  38. 3GPP, “Multiplexing and channel coding (FDD) (release 5),” Technical Specification TS 25.212 v5.3.0, Group Radio Access Network, 3rd Generation Partnership Project, Cedex, France, 2002. View at Google Scholar
  39. P. Jääskeläinen, V. Guzma, A. Cilio, T. Pitkänen, and J. Takala, “Codesign toolset for application-specific instruction-set processors,” in Multimedia on Mobile Devices, vol. 6507 of Proceedings of SPIE, pp. 1–11, San Jose, Calif, USA, January 2007. View at Publisher · View at Google Scholar
  40. G. H. Golub, Matrix Computations, John Hopkins University Press, Baltimore, Md, USA, 1989.