International Journal of Microwave Science and Technology / 2013 / Article / Fig 6

Research Article

An Inductorless Cascaded Phase-Locked Loop with Pulse Injection Locking Technique in 90nm CMOS

Figure 6

(a) Proposed differential delay cell, (b) two-stage differential VCO of MPLL with a bias-level-shift circuit.
584341.fig.006a
(a)
584341.fig.006b
(b)

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