An Inductorless Cascaded Phase-Locked Loop with Pulse Injection Locking Technique in 90 nm CMOS

Table 4

Performance comparison of PLLs.

Reference	CMOS Technology	𝑓0 [GHz]	𝑁=𝑓0/𝑓ref	𝐿in-band [dBc/Hz]	𝐿^∗normalized [dBc/Hz^2]	Power [mW]	Area [mm^2]	VCO
This work	90 nm	1.6	32	−𝟏𝟏𝟔	−𝟐𝟐𝟑	11 (sim.)	0.031	Ring
		7.2	144	−𝟏𝟎𝟏	−𝟐𝟐𝟏	25	0.11
		9.6	192	−𝟗𝟑	−𝟐𝟏𝟔	27
[11]	90 nm	20	20	−113	−229	38	0.46	LC
[18]	90 nm	9.24	35	−97	−212	56	0.09	Ring
[19]	0.18 μm	8.98	17	−110	−222	58	0.77	LC
[20]	0.18 μm	8.45	32	−98	−212	117	5.5	LC

^*Normalized in-band phase noise = 𝐿_in-band – 20log 𝑁 – 10log 𝑓_ref.