An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture

Table 1

Structures of typical RLDs.

Device	Virtex-4 (XC4VLX15) [21]	DRP-1 [8]
Logic Block structure	4-LUT × 8	8-bit ALU
	Carry logic × 2	8-bit DMU
	MULT AND × 8	Register file
	Distributed RAM 64 bit	(8 bit × 16 word)
# of LBs	112,288	512
Dedicated IP	18-bit multiplier	32-bit multiplier