Table of Contents Author Guidelines Submit a Manuscript
International Journal of Reconfigurable Computing
Volume 2008 (2008), Article ID 403086, 11 pages
http://dx.doi.org/10.1155/2008/403086
Research Article

A Game-Theoretic Approach for Run-Time Distributed Optimization on MP-SoC

1CEA /Leti-Minatec, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France
2LIRMM, University of Montpellier 2/CNRS UMR 5506, 161 rue Ada, 34392 Montpellier Cedex 5, France

Received 29 February 2008; Accepted 12 August 2008

Academic Editor: Michael Hubner

Copyright © 2008 Diego Puschini et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. G. Martin, “Overview of the MPSoC design challenge,” in Proceedings of the 43rd Annual Conference on Design Automation (DAC '06), pp. 274–279, ACM, San Francisco, Calif, USA, July 2006. View at Publisher · View at Google Scholar
  2. http://techresearch.intel.com/articles/Tera-Scale/1421.htm.
  3. W. J. Dally and B. Towles, “Route packets, not wires: on-chip interconnection networks,” in Proceedings of the 38th Annual Conference on Design Automation (DAC '01), pp. 684–689, Las Vegas, Nev, USA, June 2001.
  4. L. Benini and G. De Micheli, “Networks on chips: a new SoC paradigm,” Computer, vol. 35, no. 1, pp. 70–78, 2002. View at Publisher · View at Google Scholar
  5. J. L. Cohon, Multiobjective Programming and Planning, Academic Press, New York, NY, USA, 1978.
  6. G. M. Link and N. Vijaykrishnan, “Hotspot prevention through runtime reconfiguration in network-on-chip,” in Proceedings of the Conference on Design, Automation and Test in Europe (DATE '05), vol. 1, pp. 648–649, IEEE Computer Society, Munich, Germany, March 2005. View at Publisher · View at Google Scholar
  7. M. Ruggiero, A. Acquaviva, D. Bertozzi, and L. Benini, “Application-specific power-aware workload allocation for voltage scalable MPSoC platforms,” in Proceedings of the IEEE International Conference on Computer Design (ICCD '05), pp. 87–93, IEEE Computer Society, San Jose, Calif, USA, October 2005. View at Publisher · View at Google Scholar
  8. J. von Neumann and O. Morgenstern, Theory of Games and Economic Behavior, Princeton University Press, Princeton, NJ, USA, 1944.
  9. D. Puschini, F. Clermidy, P. Benoit, G. Sassatelli, and L. Torres, “Temperature-aware distributed run-time optimization on MP-SoC using game theory,” in Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI '08), pp. 375–380, IEEE Computer Society, Montpellier, France, April 2008.
  10. J. Donald and M. Martonosi, “Techniques for multicore thermal management: classification and new exploration,” in Proceedings of the 33rd International Symposium on Computer Architecture (ISCA '06), pp. 78–88, Boston, Mass, USA, June 2006. View at Publisher · View at Google Scholar
  11. U. Y. Ogras, R. Marculescu, P. Choudhary, and D. Marculescu, “Voltage-frequency island partitioning for GALS-based networks-on-chip,” in Proceedings of the 44th Annual Conference on Design Automation (DAC '07), pp. 110–115, ACM, San Diego, Calif, USA, June 2007.
  12. E. Beigné, F. Clermidy, S. Miermont, and P. Vivet, “Dynamic voltage and frequency scaling architecture for units integration within a GALS NoC,” in Proceedings of the 2nd ACM/IEEE International Symposium on Networks-on-Chip (NOCS '08), pp. 129–138, Newcastle upon Tyne, UK, April 2008. View at Publisher · View at Google Scholar
  13. E. Beigné, F. Clermidy, S. Miermont et al., “A fully integrated power supply unit for fine grain dvfs and leakage control validated on low-voltage srams,” in Proceeding of the 34th European Solid-State Circuits Conference (ESSCIRC '08), Edinburg, UK, September 2008.
  14. D. Lattard, E. Beigné, C. Bernard et al., “A telecom baseband circuit based on an asynchronous network-on-chip,” in Proceedings of the 54th IEEE International Solid-State Circuits Conference (ISSCC '07), pp. 258–601, San Francisco, Calif, USA, February 2007. View at Publisher · View at Google Scholar
  15. S. Murali, A. Mutapcic, D. Atienza, R. Gupta, S. Boyd, and G. De Micheli, “Temperature-aware processor frequency assignment for MPSoCs using convex optimization,” in Proceedings of the 5th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '07), pp. 111–116, ACM, Salzburg, Austria, September-October 2007. View at Publisher · View at Google Scholar
  16. M. Ruggiero, A. Guerri, D. Bertozzi, F. Poletti, and M. Milano, “Communication-aware allocation and scheduling framework for stream-oriented multi-processor systems-on-chip,” in Proceedings of the Conference on Design, Automation and Test in Europe (DATE '06), vol. 1, pp. 3–8, Munich, Germany, March 2006.
  17. M. Kandemir and G. Chen, “Locality-aware process scheduling for embedded MPSoCs,” in Proceedings of the Conference on Design, Automation and Test in Europe (DATE '05), vol. 2, pp. 870–875, IEEE Computer Society, Munich, Germany, March 2005. View at Publisher · View at Google Scholar
  18. F. Li and M. Kandemir, “Locality-conscious workload assignment for array-based computations in MPSOC architectures,” in Proceedings of the 42nd Annual Conference on Design Automation (DAC '05), pp. 95–100, ACM, Anaheim, Calif, USA, June 2005.
  19. J. Hu and R. Marculescu, “Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints,” in Proceedings of the Conference on Design, Automation and Test in Europe (DATE '04), vol. 1, pp. 234–239, IEEE Computer Society, Paris, France, February 2004. View at Publisher · View at Google Scholar
  20. E. Carvalho, N. Calazans, and F. Moraes, “Heuristics for dynamic task mapping in NoC-based heterogeneous MPSoCs,” in Proceedings of the 18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP '07), pp. 34–40, IEEE Computer Society, Porto alegre, Brazil, May 2007. View at Publisher · View at Google Scholar
  21. A. K. Coskun, T. S. Rosing, and K. Whisnant, “Temperature aware task scheduling in MPSoCs,” in Proceedings of the Conference on Design, Automation and Test in Europe (DATE '07), pp. 1659–1664, EDA Consortium, Nice, France, April 2007. View at Publisher · View at Google Scholar
  22. Ch. Ykman-Couvreur, E. Brockmeyer, V. Nollet, T. Marescaux, F. Catthoor, and H. Corporaal, “Design-time application exploration for MP-SoC customized run-time management,” in Proceedings of the International Symposium on System-on-Chip (SoC '05), pp. 66–69, Tampere, Finland, November 2005. View at Publisher · View at Google Scholar
  23. Ch. Ykman-Couvreur, V. Nollet, T. Marescaux, E. Brockmeyer, F. Catthoor, and H. Corporaal, “Pareto-based application specification for MP-SoC customized run-time management,” in Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS '06), pp. 78–84, Samos, Greece, July 2006. View at Publisher · View at Google Scholar
  24. C. Ykman-Couvreur, V. Nollet, F. Catthoor, and H. Corporaal, “Fast multi-dimension multi-choice knapsack heuristic for MP-SoC run-time management,” in Proceedings of the International Symposium on System-on-Chip (SOC '06), pp. 195–198, Tampere, Finland, November 2006. View at Publisher · View at Google Scholar
  25. P. Pillai and K. G. Shin, “Real-time dynamic voltage scaling for low-power embedded operating systems,” in Proceedings of the 18th ACM Symposium on Operating Systems Principles (SOSP '01), vol. 35, pp. 89–102, ACM, Banff, Canada, December 2001. View at Publisher · View at Google Scholar
  26. B. Knerr, M. Holzer, and M. Rupp, “Task scheduling for power optimisation of multi frequency synchronous data flow graphs,” in Proceedings of the 18th Symposium on Integrated Circuits and Systems Design (SBCCI '05), pp. 50–55, ACM, Florianopolis, Brazil, September 2005. View at Publisher · View at Google Scholar
  27. N. Hanchate and N. Ranganathan, “Simultaneous interconnect delay and crosstalk noise optimization through gate sizing using game theory,” IEEE Transactions on Computers, vol. 55, no. 8, pp. 1011–1023, 2006. View at Publisher · View at Google Scholar
  28. J. Nash, “Non-cooperative games,” The Annals of Mathematics, vol. 54, no. 2, pp. 286–295, 1951. View at Publisher · View at Google Scholar · View at Zentralblatt MATH
  29. M. J. Osborne and A. Rubinstein, A Course in Game Theory, MIT Press, Cambridge Mass, USA, 1994.
  30. K. Niyogi and D. Marculescu, “Speed and voltage selection for GALS systems based on voltage/frequency islands,” in Proceedings of the Conference on Asia South Pacific Design Automation (ASP-DAC '05), pp. 292–297, ACM, Shanghai, China, January 2005. View at Publisher · View at Google Scholar
  31. W. Hung, C. Addo-Ouaye, T. Theocharides, Y. Xie, N. Vijaykrishnan, and M. J. Irwin, “Thermal-aware IP virtualization and placement for networks-on-chip architecture,” in Proceedings of the IEEE International Conference on Computer Design (ICCD '04), pp. 430–437, IEEE Computer Society, San Jose, Calif, USA, October 2004. View at Publisher · View at Google Scholar
  32. N. Saint-Jean, P. Benoit, G. Sassatelli, L. Torres, and M. Robert, “Application case studies on HS-scale, a MP-SOC for embbeded systems,” in Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS '07), pp. 88–95, Samos, Greece, July 2007. View at Publisher · View at Google Scholar
  33. N. Saint-Jean, G. Sassatelli, P. Benoit, L. Torres, and M. Robert, “HS-scale: a hardware-software scalable MP-SOC architecture for embedded systems,” in Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), pp. 21–28, IEEE Computer Society, Porto Alegre, Brazil, March 2007. View at Publisher · View at Google Scholar
  34. J. W. Herrmann, “A genetic algorithm for minimax optimization problems,” in Proceedings of the Congress on Evolutionary Computation (CEC '99), vol. 2, pp. 1099–1103, IEEE Press, Washington, DC, USA, July 1999. View at Publisher · View at Google Scholar