International Journal of Reconfigurable Computing / 2008 / Article / Fig 5

Research Article

The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units

Figure 5

Different pin positions in EB.
736203.fig.005a
(a) CLBs connect to one side of EB with highest I/O denisty
736203.fig.005b
(b) CLBs connect to two sides of EB
736203.fig.005c
(c) CLBs connect to three sides of EB
736203.fig.005d
(d) CLBs connect to four sides of EB with lowest I/O denisty

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