Table 4: Minimum channel width (number of wires) for different I/O positions for single EB-type FPGA as shown in Figure 5. The percentage shows the deviation from the 1 side result.

Circuits1 side2 sides3 sides4 sides

bgm44 (0%)44 (0%)30 (−32%)27 (−39%)
dscg43 (0%)44 (2%)30 (−30%)33 (−23%)
bfly44 (0%)44 (0%)38 (−14%)37 (−16%)
ode43 (0%)44 (2%)35 (−19%)33 (−23%)
mm345 (0%)45 (0%)29 (−36%)30 (−33%)
fir442 (0%)44 (5%)32 (−24%)29 (−31%)

Average43.5 (0%)44.2 (1.6%)32.3 (−26%)31.5 (−28%)