International Journal of Reconfigurable Computing / 2008 / Article / Tab 5

Research Article

The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units

Table 5

Minimum channel width of multiple EB types FPGA.

CircuitsMinimum channel widthChannel width increase (%) (I/O pos.: 4 sides, type 3 in Figure 4)

bgm270
dscg356.06
bfly5035.14
ode369.09
mm3326.66
fir43313.79

Average35.511.79

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