Research Article

Architecture-Level Exploration of Alternative Interconnection Schemes Targeting 3D FPGAs: A Software-Supported Methodology

Table 3

Comparison results between MCNC benchmarks: implementation in 2D and 3D FPGA architecture with three functional layers as well as and TSVs.

BenchmarkWirelength ( )Delay (  sec)Power (  Watt)
2D3D3D2D3D3D2D3D3D

alu437.8135.6537.0973.745.947.2115.9367.2273.52
apex258.9956.0653.1610553.450.5106.9952.9154.69
apex437.7638.1637.9279.243.741.1068.3838.9134.77
bigkey32.7148.5743.6838.123.022.2317.79180.60172.70
clma430.44294.60280.50170114103456.00323.02283.89
des52.7045.4443.8263.443.339.2231.04142.05158.61
diffeq34.8836.3131.0858.860.360.4104.1497.05116.54
dsip29.9035.4633.6931.922.020.2349.29235.90194.56
elliptic102.2492.1594.9189.192.683.7272.58280.38266.23
ex101036.9033.7831.4754.047.746.7103.9583.4490.77
ex5p129.65167.00146.4216373.573.8117.6546.7146.37
frisc174.0599.8391.26100110105152.35160.13163.65
misex339.3138.2637.8886.940.346.486.9341.1241.80
pdc238.78173.32160.3715379.778.3179.8286.1182.73
s29855.8544.6542.3018792.587.178.6836.5341.72
s38417172.01169.52155.9790.264.174.8284.25185.8425.92
s38584129.14152.62136.3997.360.855.6264.54183.45129.86
Seq52.8054.4948.7466.647.644.8132.37105.9389.05
Spla148.19113.47125.0313264.866.4125.7964.5861.77
Tseng25.8923.8521.0763.954.855.593.7671.5271.60
Average101.0087.65982.6495.261.760.1182.00124.00122.00
Ratio1.000.870.821.000.650.631.000.680.67