International Journal of Reconfigurable Computing

Research Article

Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs

Algorithm 1

Case when the size of 𝐴 𝐿 is 1 bit
 If 𝐴 𝐿 = 0 then
   PS = AH Γ— BL Γ— 21
  Else
   PS = AH Γ— BL Γ— 21 + B
  End if
  A Γ— B = AH Γ— BH Γ— 2t + PS
Case when the size of 𝐴 𝐿 is 2 bits
  If AL = 00 then
   PS = AH Γ— BL Γ— 22
  Else if AL = 01 then
   PS = AH Γ— BL Γ— 22 + B
  Else if AL = 10 then
   PS = AH Γ— BL Γ— 22 + B Γ— 21
  Else
   PS = AH Γ— BL Γ— 22 + B Γ— 21 + B
  End if
  A Γ— B = AH Γ— BH Γ— 2(t + 1) + Ps
Case when the size of 𝐴 𝐿 is 3 bits
  If AL = 000 then
   PS = AH Γ— BL Γ— 23
  Else if AL = 001 then
   PS = AH Γ— BL Γ— 23 + B
  Else if AL = 010 then
   PS = AH Γ— BL Γ— 23 + B Γ— 21
  Else if AL = 011 then
   PS = AH Γ— BL Γ— 23 + B Γ— 21 + B
  Else if AL = 100 then
   PS = AH Γ— BL Γ— 23 + B Γ— 22
  Else if AL = 101 then
   PS = AH Γ— BL Γ— 23 + B Γ— 22 + B
  Else if AL = 110 then
   PS = AH Γ— BL Γ— 23 + B Γ— 22 + B Γ— 21
  Else
   PS = AH Γ— BL Γ— 23 + B Γ— 22 + B Γ— 21 + B
  End if
  A Γ— B = AH Γ— BH Γ— 2(t + 2) + Ps