Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="145130.fig.010a" src="https://static.hindawi.com/articles/ijrc/volume-2009/145130/figures/145130.fig.010a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>Delay</td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="145130.fig.010b" src="https://static.hindawi.com/articles/ijrc/volume-2009/145130/figures/145130.fig.010b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>Area</td></tr></table></td></tr><tr class="fig-image" id="c"><td><img alt="145130.fig.010c" src="https://static.hindawi.com/articles/ijrc/volume-2009/145130/figures/145130.fig.010c.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(c) </b>DSP blocks</td></tr></table></td></tr></table>

<table>Comparison of the results.</table>

International Journal of Reconfigurable Computing

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Figure 10

Figure 10: Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs 