Pipeline FFT Architectures Optimized for FPGAs

Table 4

Implementation results on Spartan-3 devices.

	Point	Input data	Twiddle factor	Slices	Block	Max. speed	Latency	Transform time		Throughput	Throughput/area
	size	width	width		RAM	(MHz)	(cycles)	Cycles	Time (𝜇s)	(MS/s)	(MS/s/slice)
R4SDC	16	16	16	468	2	108.20	21	16	0.15	108.20	0.231
	64	16	16	952	2	107.23	73	64	0.60	107.23	0.113
	256	16	16	1990	3	111.98	269	256	2.76	111.98	0.056
	1024	16	16	4409	8	123.84	1041	1024	8.27	123.84	0.028
R2^2SDF	16	16	16	427	2	121.24	22	16	0.13	121.24	0.284
	64	16	16	810	2	98.14	74	64	0.65	98.14	0.121
	256	16	16	1303	3	98.73	270	256	2.59	98.73	0.076
	1024	16	16	2802	8	95.25	1042	1024	10.75	95.25	0.034