International Journal of Reconfigurable Computing / 2009 / Article / Tab 4

Research Article

Pipeline FFT Architectures Optimized for FPGAs

Table 4

Implementation results on Spartan-3 devices.

PointInput dataTwiddle factorSlicesBlockMax. speedLatencyTransform timeThroughputThroughput/area
sizewidthwidthRAM(MHz)(cycles)CyclesTime ( s)(MS/s)(MS/s/slice)

R4SDC1616164682108.2021160.15108.200.231
6416169522107.2373640.60107.230.113
256161619903111.982692562.76111.980.056
1024161644098123.84104110248.27123.840.028

R22SDF1616164272121.2422160.13121.240.284
641616810298.1474640.6598.140.121
25616161303398.732702562.5998.730.076
102416162802895.251042102410.7595.250.034

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