Pipeline FFT Architectures Optimized for FPGAs

Table 5

Implementation results on Virtex-4 devices.

	Point	Input data	DSP48	Slices	Block	Max. speed	Latency	Transform time		Throughput	Throughput/area
	size	width			RAM	(MHz)	(cycles)	Cycles	Time (𝜇s)	(MS/s)	(MS/s/slice)
R4SDC	16	16	4	530	1	236.7	21	16	0.07	236.7	0.447
	64	16	8	803	2	236.4	73	64	0.27	236.4	0.294
	256	16	12	1370	3	218.9	269	256	1.17	218.9	0.160
	1024	16	16	3064	8	219.2	1041	1024	4.67	219.2	0.072
R2^2SDF	16	16	4	517	1	237.9	22	16	0.07	237.9	0.460
	64	16	8	779	2	236.7	74	64	0.27	236.7	0.304
	256	16	12	1234	3	236.7	270	256	1.08	236.7	0.192
	1024	16	16	2256	8	235.6	1042	1024	4.35	235.6	0.104