International Journal of Reconfigurable Computing / 2009 / Article / Tab 5

Research Article

Pipeline FFT Architectures Optimized for FPGAs

Table 5

Implementation results on Virtex-4 devices.

PointInput dataDSP48SlicesBlockMax. speedLatencyTransform timeThroughputThroughput/area
sizewidthRAM(MHz)(cycles)CyclesTime ( s)(MS/s)(MS/s/slice)

641688032236.473640.27236.4 0.294
256161213703218.92692561.17218.9 0.160
1024161630648219.2104110244.67219.2 0.072

256161212343236.72702561.08236.7 0.192
1024161622568235.6104210244.35235.6 0.104

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