A Message-Passing Hardware/Software Cosimulation Environment for Reconfigurable Computing Systems

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="376232.fig.006a" src="https://static.hindawi.com/articles/ijrc/volume-2009/376232/figures/376232.fig.006a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>One single ModelSim process is executed by a single CPU.</td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="376232.fig.006b" src="https://static.hindawi.com/articles/ijrc/volume-2009/376232/figures/376232.fig.006b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>Multiple ModelSim processes take advantage of multicore processors.</td></tr></table></td></tr></table>

<table>Two options to simulate multiple M2 Module Stacks.</table>

International Journal of Reconfigurable Computing

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Figure 6

Figure 6: A Message-Passing Hardware/Software Cosimulation Environment for Reconfigurable Computing Systems 