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International Journal of Reconfigurable Computing
Volume 2009, Article ID 408605, 15 pages
Research Article

High level modeling of Dynamic Reconfigurable FPGAs

INRIA Lille Nord Europe, Laboratoire d'Informatique Fondamentale de Lille (LIFL), Centre national de la recherche scientifique (CNRS), University of Lille, 59650 Lille, France

Received 31 December 2008; Accepted 26 March 2009

Academic Editor: J. Manuel Moreno

Copyright © 2009 Imran Rafiq Quadri et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


As System-on-Chip (SoC) based embedded systems have become a defacto industry standard, their overall design complexity has increased exponentially in recent years, necessitating the introduction of new seamless methodologies and tools to handle the SoC codesign aspects. This paper presents a novel SoC co-design methodology based on Model Driven Engineering and the Modeling and Analysis of Real-Time and Embedded Systems (MARTE) standard, permitting us to raise the abstraction levels and allows to model fine grain reconfigurable architectures such as FPGAs. Extensions of this methodology have enabled us to integrate new features such as Partial Dynamic Reconfiguration supported by Modern FPGAs. The overall objective is to carry out system modeling at a high abstraction level expressed in a graphical language like Unified Modeling Language (UML) and afterwards transformation of these models automatically generate the necessary code for FPGA synthesis.