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International Journal of Reconfigurable Computing
Volume 2009, Article ID 514754, 9 pages
Research Article

Speeding Up FPGA Placement via Partitioning and Multithreading

Electrical and Computer Engineering, North Dakota State University, Fargo, ND 58108-6050, USA

Received 5 June 2009; Revised 15 October 2009; Accepted 12 November 2009

Academic Editor: Marco Platzner

Copyright © 2009 Cristinel Ababei. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


One of the current main challenges of the FPGA design flow is the long processing time of the placement and routing algorithms. In this paper, we propose a hybrid parallelization technique of the simulated annealing-based placement algorithm of VPR developed in the work of Betz and Rose (1997). The proposed technique uses balanced region-based partitioning and multithreading. In the first step of this approach placement subproblems are created by partitioning and then processed concurrently by multiple worker threads that are run on multiple cores of the same processor. Our main goal is to investigate the speedup that can be achieved with this simple approach compared to previous approaches that were based on distributed computing. The new hybrid parallel placement algorithm achieves an average speedup of using four worker threads, while the total wire length and circuit delay after routing are minimally degraded.