Table 2: Synthesis results for a block of cells.

block hardware resource utilization
( groups of cells)
Xilinx FPGA XC4VLX160ff1513-12

Number of Slice Flip Flops 25,397/135,168 (18.79%)
Number of 4 input LUTs 54,315/135,168 (40.18%)
Number of occupied Slices 39,728/67,584 (58.78%)
Frequency 100 MHz