Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs

Figure 6

UWL versus MWL: homogeneous implementations (I).

(a) ITU, 𝜎²=10⁻¹

(b) ITU, 𝜎²=10⁻¹, 𝜆=9

(c) LAT₃, 𝜎²=10⁻⁵

(d) LAT₃, 𝜎²=10⁻⁵, 𝜆=22