Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs

Table 1

Simulated annealing parameters and conditions.

𝜆	Latency constraint (in clock cycles)
𝛼𝑇	Annealing factor (0.95)
|𝑂|	Number of operations in algorithm
Equilibrium state	Accepted>|𝑂|×|𝑂|
Frozen state	Iterations>𝑘⋅|𝑂|×|𝑂|, 𝑘>1.0
	3 consecutive times
Restart condition	𝐀last>1.5⋅𝐀min