Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs

Table 5

MWL synthesis: homogeneous versus heterogeneous architectures.

Bench.	𝜎^2	‖𝐀‖∞ %
		Min	Max	Mean
ITU	10^−1	40.73	52.69	51.60
	10^−2	43.29	53.98	53.01
	10^−3	50.45	54.76	54.32
LAT3	10^−3	42.68	43.09	42.72
	10^−4	39.36	39.36	39.36
	10^−5	38.73	39.74	38.82
IIR4	10^−3	34.83	44.77	36.04
	10^−4	32.92	48.23	35.96
	10^−5	33.21	48.79	35.79
FIR8	10^−3	21.42	41.46	28.37
	10^−4	27.02	44.68	33.24
	10^−5	27.46	44.62	33.52
All		21.42	54.76	40.23