Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs

Table 6

Complete versus simplified cost estimation: area improvement (%).

Arch.	Bench.	Area improvement
		Min	Max	Mean
HOM	ITU	0.00	0.95	0.30
	LAT3	0.71	3.50	1.53
	IIR4	0.00	5.35	1.26
	FIR8	0.00	1.77	0.31
HET	ITU	0.00	25.85	1.89
	LAT3	1.15	5.77	2.52
	IIR4	0.00	35.57	8.09
	FIR8	0.00	8.11	0.83
All		0.00	35.57	2.09