International Journal of Reconfigurable Computing / 2009 / Article / Tab 4

Research Article

Analysis and Design of a Context Adaptable SAD/MSE Architecture

Table 4

MPESA throughput (in terms of number of pixels per clock cycle).

Search pattern Number of searches TotalLatency(BufNodes) TputMPESA

Full search 16 31 107.8
Diamond search 8 30 55.35
Hexagon search 6 29 42.67
Big cross search 12 50 53.9

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