International Journal of Reconfigurable Computing / 2009 / Article / Tab 5

Research Article

Analysis and Design of a Context Adaptable SAD/MSE Architecture

Table 5

Illustration of the MPESA operation for block size (3 3) on the first set of candidate subblocks.

Control step OpMPE( ,16) Operation of one MPE Num DelayY NumDelay InterSAD IsFirstPEInCol IsFirstPEInRow

16 ; 0 na 1 na

17 ; 1 na 0 na

18 ; 2 na 0 na

19 ; na 0 na 1

20 ; na 1 na 0

21 ; na 2 na 0

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