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International Journal of Reconfigurable Computing
Volume 2009, Article ID 912301, 10 pages
Research Article

A System on a Programmable Chip Architecture for Data-Dependent Superimposed Training Channel Estimation

1Computer Science Department, National Institute of Astrophysics, Optics and Electronics, CP 72840, Puebla, Mexico
2Section of Communications, CINVESTAV-IPN, CP 07360, Mexico City, Mexico

Received 25 December 2008; Accepted 25 May 2009

Academic Editor: Peter Zipf

Copyright © 2009 Fernando Martín del Campo et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Channel estimation in wireless communication systems is usually accomplished by inserting, along with the information, a series of known symbols, whose analysis is used to define the parameters of the filters that remove the distortion of the data. Nevertheless, a part of the available bandwidth has to be destined to these symbols. Until now, no alternative solution has demonstrated to be fully satisfying for commercial use, but one technique that looks promising is superimposed training (ST). This work describes a hybrid software-hardware FPGA implementation of a recent algorithm that belongs to the ST family, known as Data-dependent Superimposed Training (DDST), which does not need extra bandwidth for its training sequences (TS) as it adds them arithmetically to the data. DDST also adds a third sequence known as data-dependent sequence, that destroys the interference caused by the data over the TS. As DDST's computational burden is too high for the commercial processors used in mobile systems, a System on a Programmable Chip (SOPC) approach is used in order to solve the problem.