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International Journal of Reconfigurable Computing
Volume 2010, Article ID 159367, 13 pages
http://dx.doi.org/10.1155/2010/159367
Research Article

Mechanism of Resource Virtualization in RCS for Multitask Stream Applications

1Embedded Reconfigurable Systems Laboratory (ERSL), Department of Electrical and Computer Engineering, Ryerson University, Toronto, ON, M5B2K3, Canada
2MDA Space Missions, Brampton, ON, L6S4J3, Canada
3Department of Aerospace Engineering, Ryerson University, Toronto, ON, M5B2K3, Canada

Received 8 March 2010; Accepted 14 September 2010

Academic Editor: Lionel Torres

Copyright © 2010 L. Kirischian et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. E. Caspi, M. Chu, R. Huang, J. Wawrzynek, J. Yeh, and A. DeHon, “Stream computations organized for reconfigurable execution (SCORE),” in Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing, pp. 605–614, Springer, Berlin, Germany, 2000. View at Google Scholar
  2. S. Wallner, “A reconfigurable multi-threaded architecture model,” in Advances in Computer Systems Architecture, pp. 193–207, Springer, Berlin, Germany, 2003. View at Google Scholar
  3. M. Mishra and S. C. Goldstein, “Virtualization on the Tartan reconfigurable architecture,” in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL '07), pp. 323–330, Amsterdam, The Netherlands, August 2007. View at Publisher · View at Google Scholar · View at Scopus
  4. S. C. Goldstein, H. Schmit, M. Budiu, S. Cadambi, M. Matt, and R. R. Taylor, “PipeRench: a reconfigurable architecture and compiler,” Computer, vol. 33, no. 4, pp. 70–77, 2000. View at Publisher · View at Google Scholar · View at Scopus
  5. L. Kirischian, V. Geurkov, V. Kirischian, and I. Terterian, “Multi-parametric optimisation of the modular computer architecture,” International Journal of Technology, Policy and Management, vol. 6, no. 3, pp. 327–346, 2006. View at Publisher · View at Google Scholar
  6. H. Kalte, G. Lee, M. Porrmann, and U. Rückert, “REPLICA: a bitstream manipulation filter for module relocation in partial reconfigurable systems,” in Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium, pp. 151–158, Denver, Colo, USA, 2005.
  7. F. Ferrandi, M. Novati, M. Morandi, M. D. Santambrogio, and D. Sciuto, “Dynamic reconfiguration: core relocation via partial bitstreams filtering with minimal overhead,” in Proceedings of the International Symposium on System-on-Chip (SOC '06), pp. 1–4, Tampere, Finland, 2006. View at Publisher · View at Google Scholar
  8. S. Corbetta, F. Ferrandi, M. Morandi, M. Novati, M. D. Santambrogio, and D. Sciuto, “Two novel approaches to online partial bitstream relocation in a dynamically reconfigurable system,” in Proceedings of the IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (VLSI '07), pp. 457–458, Porto Alegre, Brazil, March 2007. View at Publisher · View at Google Scholar · View at Scopus
  9. T. Becker, W. Luk, and P. Y.K. Cheung, “Enhancing relocatability of partial bitstreams for run-time reconfiguration,” in Proceedings of the IEEE Symposium on Field-Programme Custom Computing Machines (FCCM '07), pp. 35–44, Napa, Calif, USA, 2007. View at Publisher · View at Google Scholar
  10. M. Hübner, C. Schuck, M. Kühnle, and J. Becker, “New 2-dimensional partial dynamic reconfiguration techniques for real-time adaptive microelectronic circuits,” in Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, vol. 2006, pp. 97–102, Karlsruhe, Germany, 2006. View at Publisher · View at Google Scholar
  11. C. Bobda, M. Majer, A. Ahmadinia, T. Haller, A. Linarth, and J. Teich, “The Erlangen slot machine: increasing flexibility in FPGA-based reconfigurable platforms,” in Proceedings of the IEEE International Conference on Field Programmable Technology, pp. 37–42, Singapore, December 2005. View at Publisher · View at Google Scholar · View at Scopus
  12. L. Kirischian, V. Geurkov, I. Terterian, V. Kirischian, and J. Kleiman, “Multilevel radiation protection of partially reconfigurable field programmable gate array devices,” Journal of Spacecraft and Rockets, vol. 43, no. 3, pp. 523–529, 2006. View at Publisher · View at Google Scholar · View at Scopus
  13. Xilinx, “Early access partial reconfiguration user guide, 1.2 edn,” 2008.
  14. L. P. Carloni, K. L. McMillan, and A. L. Sangiovanni-Vincentelli, “Theory of latency-insensitive design,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 9, pp. 1059–1076, 2001. View at Publisher · View at Google Scholar · View at Scopus
  15. Xilinx, “Virtex 4 FPGA user guide, 2.5 edn,” 2008.
  16. Xilinx, “Virtex-4 FPGA configuration user guide, 1.1 edn,” 2008.