High-Speed FPGA 10's Complement Adders-Subtractors

Table 1

Time delays (nsec) for different adders in Virtex-4 -11.

N	N-digit BCD adder				M	M-bit Binary
	Ripple	PG_a	PG_b	PG_c
8	14	5.8	6.7	4.5	27	2.7
12	20	6.0	6.8	4.8	40	3.2
16	27	6.1	7.0	5.1	54	3.7
24	40	6.4	7.3	5.7	80	4.7
32	53	6.7	7.6	6.3	107	5.7
40	66	7.0	7.9	6.9	133	6.6
48	79	7.3	8.2	7.5	160	7.6
64	105	7.9	8.7	8.7	213	9.6
96	—	9.1	9.9	11.0	319	13.5
128	—	10.3	11.1	13.4	426	17.5