High-Speed FPGA 10's Complement Adders-Subtractors

Table 2

Area (in LUTs) for different adder’s size in Virtex-4.

Adder Circuit	# LUT’s
Ripple	8 × 𝑁
PG_a	10 × 𝑁
PG_b	18 × 𝑁
PG_c	16 × 𝑁
Binary	⌈3.32×𝑁⌉