High-Speed FPGA 10's Complement Adders-Subtractors

Table 4

Delays in ns for decimal and binary adder-subtractor in Virtex-5 -2.

N (BCD digits)	AS-I	AS-II	M (bits)	Binary Add-Sub
8	3.8	3.8	27	2.1
16	4.1	4.0	54	2.6
32	4.7	5.0	107	3.8
48	5.3	5.2	160	5.2
64	5.7	5.5	213	6.6
96	6.3	6.2	319	8.8