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International Journal of Reconfigurable Computing
Volume 2010, Article ID 475620, 10 pages
http://dx.doi.org/10.1155/2010/475620
Research Article

Multiloop Parallelisation Using Unrolling and Fission

1Faculty of Information Technology, Macau University of Science and Technology, Taipa, Macau, China
2Department of Computing, Imperial College London, London, UK
3School of Electrical and Information Engineering, University of Sydney, Sydney, NSW, Australia

Received 1 July 2009; Accepted 19 October 2009

Academic Editor: Valentin Obac Roda

Copyright © 2010 Yuet Ming Lam et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. R. Camposano, “Path-based scheduling for synthesis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 10, no. 1, pp. 85–93, 1991. View at Publisher · View at Google Scholar · View at Scopus
  2. M. Rahmouni and A. A. Jerraya, “Formulation and evaluation of scheduling techniques for control flow graphs,” in Proceedings of the European Design Automation Conference (EURO-DAC '95), pp. 386–391, Brighton, UK, September 1995. View at Scopus
  3. A. Hatanaka and N. Bagherzadeh, “A modulo scheduling algorithm for a coarse-grain reconfigurable array template,” in Proceedings of the 21st International Parallel and Distributed Processing Symposium (IPDPS '07), pp. 1–8, 2007. View at Publisher · View at Google Scholar · View at Scopus
  4. F. E. Sandnes and O. Sinnen, “A new strategy for multiprocessor scheduling of cyclic task graphs,” International Journal of High Performance Computing and Networking, vol. 3, no. 1, pp. 62–71, 2005. View at Google Scholar
  5. T. Yang and C. Fu, “Heuristic algorithms for scheduling iterative task computations on distributed memory machines,” IEEE Transactions on Parallel and Distributed Systems, vol. 8, no. 6, pp. 608–622, 1997. View at Google Scholar · View at Scopus
  6. M. Weinhardt and W. Luk, “Pipeline vectorization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 2, pp. 234–248, 2001. View at Publisher · View at Google Scholar · View at Scopus
  7. P. Šůcha, Z. Hanzálek, A. Heřmánek, and J. Schier, “Efficient FPGA implementation of equalizer for finite interval constant modulus algorithm,” in Proceedings of the International Symposium on Industrial Embedded Systems (IES '06), pp. 1–10, Antibes Juan-les-Pins, France, October 2006. View at Publisher · View at Google Scholar · View at Scopus
  8. H. Styles, D. B. Thomas, and W. Luk, “Pipelining designs with loop-carried dependencies,” in Proceedings of the IEEE International Conference on Field-Programmable Technology (FPT '04), pp. 255–262, 2004. View at Scopus
  9. M. Kaul, R. Vemuri, S. Govindarajan, and I. Ouaiss, “An automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of DSP applications,” in Proceedings of the 36th Annual ACM/IEEE Design Automation Conference, pp. 616–622, 1999. View at Scopus
  10. J. M. P. Cardoso, “Loop dissevering: a technique for temporally partitioning loops in dynamically reconfigurable computing platforms,” in Proceedings of the International Parallel and Distributed Processing Symposium, pp. 22–26, April 2003. View at Publisher · View at Google Scholar
  11. Y. M. Lam, J. G. F. Coutinho, W. Luk, and P. H. W. Leong, “Mapping and scheduling with task clustering for heterogeneous computing systems,” in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL '08), pp. 275–280, Berlin, Germany, September 2008. View at Publisher · View at Google Scholar · View at Scopus
  12. Y. M. Lam, J. G. F. Coutinho, W. Luk, and P. H. W. Leong, “Unrolling-based loop mapping and scheduling,” in Proceedings of the International Conference on Field-Programmable Technology (ICFPT '08), pp. 321–324, Taipei, Taiwan, December 2008. View at Publisher · View at Google Scholar · View at Scopus
  13. W. Luk, J. G. F. Coutinho, T. Todman et al., “A high-level compilation toolchain for heterogeneous systems,” in Proceedings of the IEEE International SOC Conference, pp. 9–18, Belfast, Ireland, September 2009.
  14. L. Rabiner and B. H. Juang, Fundamentals of Speech Recognition, Prentice-Hall, Englewood Cliffs, NJ, USA, 1993.
  15. LDC, http://www.ldc.upenn.edu/.
  16. S. M. Smith and J. M. Brady, “SUSAN—a new approach to low level image processing,” International Journal of Computer Vision, vol. 23, no. 1, pp. 45–78, 1997. View at Google Scholar · View at Scopus
  17. S. J. Aarseth, “Direct methods for N-body simulation,” in Multiple Time Scales, Academic Press, New York, NY, USA, 2001. View at Google Scholar