3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans

<table>Latency comparison for 2D and 2-layer implementations of <i>hp</i>.</table>

International Journal of Reconfigurable Computing

Figure 19: 3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans 