3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans

<table>Latency for 2-layer and 3-layer implementations of <i>apte</i>.</table>

International Journal of Reconfigurable Computing

Figure 23: 3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans 