3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans

<table>Illustration of the routers assignment step on a testcase with 6 IP/cores and a regular mesh network of <svg height="11.125" id="M24" style="vertical-align:-0.1638pt" version="1.1" viewbox="0 0 33.974998 11.125" width="33.974998" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
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</svg> routers.</table>

International Journal of Reconfigurable Computing

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Figure 7

Figure 7: 3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans 