Traversal Caches: A Framework for FPGA Acceleration of Pointer Data Structures

Algorithm 2

Pseudocode of the software portion of the (similarity-based) traversal cache implementation of Barnes-Hut.

def BarnesHut_{TC_SW} (TimeSteps, Bodies):

 Tree = BuildTree (Bodies)

 for # of TimeSteps:

  Tree_Serial = SerializeTree (Tree)

  Bodies_Serial = SerializeOrderedBodies (Tree)

  PopulateCache (Bodies_Serial, Tree_Serial)

  ClearTree (Tree)

  StartFPGA ()

  while FPGABusy ():

   if FPGAHasData ():

    PartialBuildTree (Tree, ReadFPGAResults())

 return GetBodies (Tree)