Traversal Caches: A Framework for FPGA Acceleration of Pointer Data Structures

Figure 5

Simplified traversal generator logic for preorder tree traversal used to implement Barnes-Hut. The traversal generator guides exploration of the data structure for 𝑝 simultaneous traversals, minimizing accesses by coordinating multiple datapaths by selectively asserting valid[ ] using membership data from each datapath’s generator kernel on include[ ].