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International Journal of Reconfigurable Computing
Volume 2010 (2010), Article ID 697625, 17 pages
Research Article

Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs

1Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106, USA
2Cadence Design Systems, University of California, San Diego, CA 95134, USA
3Department of Computer Science and Engineering, Cadence, La Jolla, CA 92093, USA

Received 14 April 2009; Revised 13 November 2009; Accepted 17 January 2010

Academic Editor: Liam Marnane

Copyright © 2010 Shahnam Mirzaei et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


We present a method for implementing high speed finite impulse response (FIR) filters on field programmable gate arrays (FPGAs). Our algorithm is a multiplierless technique where fixed coefficient multipliers are replaced with a series of add and shift operations. The first phase of our algorithm uses registered adders and hardwired shifts. Here, a modified common subexpression elimination (CSE) algorithm reduces the number of adders while maintaining performance. The second phase optimizes routing delay using prelayout wire length estimation techniques to improve the final placed and routed design. The optimization target platforms are Xilinx Virtex FPGA devices where we compare the implementation results with those produced by Xilinx Coregen, which is based on distributed arithmetic (DA). We observed up to 50% reduction in the number of slices and up to 75% reduction in the number of look up tables (LUTs) for fully parallel implementations compared to DA method. Also, there is 50% reduction in the total dynamic power consumption of the filters. Our designs perform up to 27% faster than the multiply accumulate (MAC) filters implemented by Xilinx Coregen tool using DSP blocks. For placement, there is a saving up to 20% in number of routing channels. This results in lower congestion and up to 8% reduction in average wirelength.