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International Journal of Reconfigurable Computing
Volume 2010, Article ID 697625, 17 pages
http://dx.doi.org/10.1155/2010/697625
Research Article

Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs

1Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106, USA
2Cadence Design Systems, University of California, San Diego, CA 95134, USA
3Department of Computer Science and Engineering, Cadence, La Jolla, CA 92093, USA

Received 14 April 2009; Revised 13 November 2009; Accepted 17 January 2010

Academic Editor: Liam Marnane

Copyright © 2010 Shahnam Mirzaei et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Shahnam Mirzaei, Ryan Kastner, and Anup Hosangadi, “Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs,” International Journal of Reconfigurable Computing, vol. 2010, Article ID 697625, 17 pages, 2010. https://doi.org/10.1155/2010/697625.