Montgomery Modular Multiplication on Reconfigurable Hardware: Systolic versus Multiplexed Implementation

Table 1

Proposed architectures synthesis.

Virtex-4
𝑛	𝑘	Slices	Clock cycles	DSP48	Freq. (MHz)	BRAM (Bytes)
Systolic architecture
512	16	3322	192	68	110	128
512	32	4199	96	36	78	128
1024	16	7012	384	130	110	256
Multiplexed architecture
512	16	2199	256	32	120	256
512	32	2499	128	32	80	256
1024	16	4876	512	64	120	512
1024	32	5118	256	64	80	512
Virtex-5
Systolic architecture
512	16	3205	192	68	130	128
512	32	3876	96	36	95	128
1024	16	6642	384	130	130	256
Multiplexed architecture
512	16	2078	256	32	120	256
512	32	2370	128	32	90	256
1024	16	4876	512	64	120	512
1024	32	5005	256	64	90	512