Research Article
High-Level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis
Table 5
Individual backprojection timing assertion overhead.
| | EP3SE260 | Original | Assert | Difference |
| | Logic used | 48285 | 49702 | +1417 | | (out of 203520) | (23.72%) | (24.42%) | (+0.70%) |
| | Comb. ALUT | 32962 | 33132 | +170 | | (out of 203520) | (16.20%) | (16.28%) | (+0.08%) |
| | Registers | 44098 | 44595 | +497 | | (out of 203520) | (21.67%) | (21.91%) | (+0.24%) | | Block RAM | 7114752 | 7114752 | 0 | | (15040512 bits) | (47.30%) | (47.30%) | (0%) |
| | Block interconnect | 101317 | 102740 | +1423 | | (out of 694728) | (14.58%) | (14.79%) | (+0.20%) |
| | Frequency (MHz) | 131.9 | 132.5 | +0.6 (+0.45%) |
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