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International Journal of Reconfigurable Computing
Volume 2011 (2011), Article ID 425401, 15 pages
Research Article

AADL Extension to Model Classical FPGA and FPGA Embedded within a SoC

1Lab-STICC/CNRS UMR3192, Université de Bretagne-Sud, Centre de recherche, BP 92116, 56321 Lorient Cedex, France
2Cairn Inria/Irisa, Université de Rennes 1, ENSSAT, 6 rue de Kerampont, BP 80518, 22305 Lannion, France
3Leat/CNRS UMR6071, Université de Nice-Sophia Antipolis, 250 rue Albert Einstein, Bt. 4, 06560 Valbonne, France
4InPixal, Immeuble “Le Germanium”, 80 avenue des Buttes de Cosmes, 35700 Rennes, France

Received 26 November 2010; Revised 23 March 2011; Accepted 25 May 2011

Academic Editor: Koen L. M. Bertels

Copyright © 2011 Dominique Blouin et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Dominique Blouin, Daniel Chillet, Eric Senn, Sébastien Bilavarn, Robin Bonamy, and Christian Samoyeau, “AADL Extension to Model Classical FPGA and FPGA Embedded within a SoC,” International Journal of Reconfigurable Computing, vol. 2011, Article ID 425401, 15 pages, 2011. doi:10.1155/2011/425401