Research Article
AADL Extension to Model Classical FPGA and FPGA Embedded within a SoC
Table 2
Example of possible combinations of task allocations within the execution platform when considering that the processor is always active even if no software task have to be executed. Note that the first and last rows are those which are not acceptable due to the total task execution delays () or the total task areas (). Remarks: is incorrect due to the total execution time greater than the period of tasks; is incorrect due to the total area greater than the global area in the reconfigurable space.
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