Research Article

Sustainable Modular Adaptive Redundancy Technique Emphasizing Partial Reconfiguration for Reduced Power Consumption

Table 3

System modules implementation.

ModuleImplementation platform

Organic layerML402 (lower board of VSK) with Virtex-4 FPGA (XCV4SX35)
Video capturing/bufferingVideo IO Daughter Card (VIODC)
(Upper board of VSK) with Virtex-2 PRO FPGA (XCV2P7)
HW-SW connectionJTAG-GNAT from FPGA sideXilinx Parallel port from PC side
Communication ClassMultithreaded C++ application
HIMC++ Message encoder/decoder
GUI monitorJava applet
ApplicationSobel edge detector (Verilog)
OGA engineC++ based Standard GA [21]
OGA interfaceC-based API (MRRA) [23]