Table of Contents Author Guidelines Submit a Manuscript
International Journal of Reconfigurable Computing
Volume 2011, Article ID 452589, 17 pages
http://dx.doi.org/10.1155/2011/452589
Research Article

Dynamic Reconfigurable Computing: The Alternative to Homogeneous Multicores under Massive Defect Rates

Instituto de Informática, Universidade Federal do Rio Grande do Sul, 91501-970 Porto Alegre, RS, Brazil

Received 25 August 2010; Accepted 14 December 2010

Academic Editor: Michael Hübner

Copyright © 2011 Monica Magalhães Pereira and Luigi Carro. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. W. Wolf, A. A. Jerraya, and G. Martin, “Multiprocessor system-on-chip (MPSoC) technology,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 10, pp. 1701–1713, 2008. View at Publisher · View at Google Scholar · View at Scopus
  2. M. D. Hill and M. R. Marty, “Amdahl's law in the multicore era,” Computer, vol. 41, no. 7, pp. 33–38, 2008. View at Publisher · View at Google Scholar · View at Scopus
  3. M. B. Rutzig, F. Madruga, M. A. Alves et al., “TLP and ILP exploitation through a reconfigurable multiprocessor system,” in Proceedings of the IEEE International Symposium on Parallel and Distributed Processing, Workshops and Phd Forum (IPDPSW '10), April 2010. View at Publisher · View at Google Scholar · View at Scopus
  4. Samsung Electronics Co., Ltd, “Samsung S5PC100 ARM Cortex A8 based Mobile Application Processor,” 2009. View at Google Scholar
  5. iPhone, http://www.apple.com/iphone/.
  6. A. DeHon and H. Naeimi, “Seven strategies for tolerating highly defective fabrication,” IEEE Design and Test of Computers, vol. 22, no. 4, pp. 306–315, 2005. View at Publisher · View at Google Scholar · View at Scopus
  7. S. Borkar, “Microarchitecture and design challenges for gigascale integration,” in Proceedings of the 37th International Symposium on Microarchitecture (MICRO '04), p. 3, December 2004. View at Scopus
  8. I. Koren and C. M. Krishna, Fault-Tolerant Systems, Morgan Kaufmann, San Francisco, Calif, USA, 2007.
  9. S. K. Shukla and R. I. Bahar, Nano, Quantum and Molecular Computing: Implications to High Level Design and Validation, Kluwer Academic Publishers, Dordrecht, The Netherlands, 2004.
  10. D. Bernick, B. Bruckert, P. D. Vigna et al., “NonStop advanced architecture,” in Proceedings of the International Conference on Dependable Systems and Networks, pp. 12–21, July 2005. View at Scopus
  11. N. Aggarwal, P. Ranganathan, N. P. Jouppi, and J. E. Smith, “Configurable isolation: building high availability systems with commodity multi-core processors,” in Proceedings of the 34th Annual International Symposium on Computer Architecture (ISCA '07), pp. 470–481, June 2007. View at Publisher · View at Google Scholar · View at Scopus
  12. A. C. S. Beck, M. B. Rutzig, G. Gaydadjiev, and L. Carro, “Transparent reconfigurable acceleration for heterogeneous embedded applications,” in Proceedings of the Design, Automation and Test in Europe (DATE '08), pp. 1208–1213, March 2008. View at Publisher · View at Google Scholar · View at Scopus
  13. A. C. S. Beck and L. Carro, “Transparent acceleration of data dependent instructions for general purpose processors,” in Proceedings of the IFIP International Conference on Very Large Scale Integration (VLSI-SoC '07), pp. 66–71, October 2007. View at Publisher · View at Google Scholar · View at Scopus
  14. E. Stott, P. Sedcole, and P. Y. K. Cheung, “Fault tolerant methods for reliability in FPGAs,” in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL '08), pp. 415–420, September 2008. View at Publisher · View at Google Scholar · View at Scopus
  15. M. M. Pereira and L. Carro, “A dynamic reconfiguration approach for accelerating highly defective processors,” in Proceedings of the 17th IFIP/IEEE International Conference on Very Large Scale Integration, October 2009.
  16. M. R. Guthaus, J. S. Ringenberg, D. Ernst et al., “MiBench: a free, commercially representative embedded benchmark suite,” in Proceedings of the 4th IEEE International Workshop on Workload Characterization, pp. 3–14, IEEE Press, December 2001. View at Publisher · View at Google Scholar
  17. K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits,” Proceedings of the IEEE, vol. 91, no. 2, pp. 305–327, 2003. View at Publisher · View at Google Scholar · View at Scopus
  18. G. Sery, S. Borkar, and V. De, “Life is CMOS: why chase the life after?” in Proceedings of the 39th Design Automation Conference, pp. 78–83, June 2002. View at Scopus
  19. J. P. Halter and F. N. Najm, “Gate-level leakage power reduction method for ultra-low-power CMOS circuits,” in Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 475–478, May 1997. View at Scopus
  20. K. Shi and D. Howard, “Challenges in sleep transistor design and implementation in low-power designs,” in Proceedings of the 43rd Annual Conference on Design Automation, pp. 113–116, ACM Press. View at Publisher · View at Google Scholar · View at Scopus
  21. M. M. Pereira and L. Carro, “Dynamically adapted low-energy fault tolerant processors,” in NASA/ESA Conference on Adaptive Hardware and Systems (AHS '09), pp. 91–97, IEEE Press, August 2009. View at Publisher · View at Google Scholar · View at Scopus
  22. MENTOR GRAPHICS, “LeonardoSpectrumTM,” http://www.mentor.com/products/fpga/synthesis/leonardo_spectrum/.
  23. ITRS, “International Technology Roadmap for Semiconductors,” http://www.itrs.net/reports.html.
  24. K. Olukotun, L. Hammond, and J. Laudon, Chip Multiprocessor Architecture, Mark D. Hill, 2006.
  25. K. C. Yeager, “Mips R10000 superscalar microprocessor,” IEEE Micro, vol. 16, no. 2, pp. 28–40, 1996. View at Publisher · View at Google Scholar · View at Scopus
  26. F. Hatori, T. Sakurai, K. Nogami et al., “Introducing redundancy in field programmable gate arrays,” in Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 711–714, May 1993. View at Scopus
  27. F. Hanchek and S. Dutt, “Node-covering based defect and fault tolerance methods for increased yield in FPGAs,” in Proceedings of the 9th International Conference on VLSI Design, pp. 225–229, Bangalore, India, January 1996. View at Scopus
  28. J. Lach, W. H. Mangione-Smith, and M. Potkonjak, “Efficiently supporting fault-tolerance in FPGAs,” in Proceedings of the ACM/SIGDA 6th International Symposium on Field Programmable Gate Arrays (FPGA '98), pp. 105–115, Monterey, Calif, USA, February 1998. View at Scopus
  29. M. Abramovici, C. Stroud, C. Hamilton, S. Wijesuriya, and V. Verma, “Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications,” in Proceedings of the ITC International Test Conference (ITC'99), pp. 973–982, Atlantic City, NJ, USA, September 1999. View at Scopus
  30. J. M. Emmert, C. E. Stroud, J. A. Cheatham et al., “Performance penalty for fault tolerance in roving STARs,” in Proceedings of the 10th International Workshop on Field-Programmable Logic and Applications (FPL '00), pp. 545–554, Villach, Austria, August 2000. View at Publisher · View at Google Scholar
  31. J. Gebelein, H. Engel, and U. Kebschull, “FPGA fault tolerance in radiation susceptible environments,” in Radiation Effects on Components and Systems Conference (RADECS '10), Längenfeld, Austria, September 2010.
  32. T. M. Austin, “DIVA: a reliable substrate for deep submicron microarchitecture design,” in Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture (MICRO '99), pp. 196–207, November 1999. View at Scopus
  33. P. Shivakumar, S. W. Keckler, C. R. Moore, and D. Burger, “Exploiting microarchitectural redundancy for defect tolerance,” in Proceedings of the 21st International Conference on Computer Design (ICCD '03), pp. 481–488, October 2003. View at Scopus
  34. F. A. Bower, P. G. Shealy, S. Ozev, and D. J. Sorin, “Tolerating hard faults in microprocessor array structures,” in Proceedings of the International Conference on Dependable Systems and Networks, pp. 51–60, July 2004. View at Scopus
  35. J. Srinivasan, S. V. Adve, P. Bose, and J. A. Rivers, “Exploiting structural duplication for lifetime reliability enhancement,” in Proceedings of the 32nd Interntional Symposium on Computer Architecture (ISCA '05), pp. 520–531, June 2005. View at Scopus
  36. D. Sylvester, D. Blaauw, and E. Karl, “ElastIC: an adaptive self-healing architecture for unpredictable silicon,” IEEE Design and Test of Computers, vol. 23, no. 6, pp. 484–490, 2006. View at Publisher · View at Google Scholar · View at Scopus
  37. K. Constantinides, S. Plaza, J. Blome et al., “BulletProof: a defect-tolerant CMP switch architecture,” in Proceedings of the 12th International Symposium on High-Performance Computer Architecture, pp. 3–14, February 2006. View at Publisher · View at Google Scholar · View at Scopus