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International Journal of Reconfigurable Computing
Volume 2011, Article ID 483681, 12 pages
http://dx.doi.org/10.1155/2011/483681
Research Article

Floorplacement for Partial Reconfigurable FPGA-Based Systems

1Dipartimento di Elettronica e Informazione, Politecnico di Milano, 20133 Milano, Italy
2Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology, Cambridge, MA 02139, USA

Received 20 August 2010; Accepted 20 December 2010

Academic Editor: Aravind Dasu

Copyright © 2011 A. Montone et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

We presented a resource- and configuration-aware floorplacement framework, tailored for Xilinx Virtex 4 and 5 FPGAs, using an objective function based on external wirelength. Our work aims at identifying groups of Reconfigurable Functional Units that are likely to be configured in the same chip area, identifying these areas based on resource requirements, device capabilities, and wirelength. Task graphs with few externally connected RRs lead to the biggest decrease, while external wirelength in task graphs with many externally connected RRs show lower improvement. The proposed approach results, as also demonstrated in the experimental results section, in a shorter external wirelength (an average reduction of 50%) with respect to purely area-driven approaches and a highly increased probability of reuse of existing links (90% reduction can be obtained in the best case).