The Potential for a GPU-Like Overlay Architecture for FPGAs

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="514581.fig.0010a" src="https://static.hindawi.com/articles/ijrc/volume-2011/514581/figures/514581.fig.0010a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>Photon</td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="514581.fig.0010b" src="https://static.hindawi.com/articles/ijrc/volume-2011/514581/figures/514581.fig.0010b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>Matmatmult</td></tr></table></td></tr><tr class="fig-image" id="c"><td><img alt="514581.fig.0010c" src="https://static.hindawi.com/articles/ijrc/volume-2011/514581/figures/514581.fig.0010c.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(c) </b>Sgemm</td></tr></table></td></tr></table>

<table>ALU datapath utilization for the 8-bit HT interface provided with the XD1000 system.</table>

International Journal of Reconfigurable Computing

fig10

Figure 10

Figure 10: The Potential for a GPU-Like Overlay Architecture for FPGAs 