The Potential for a GPU-Like Overlay Architecture for FPGAs

Table 3

A breakdown of how each stage of an HT memory request contributes to overall access latency.

Action	Stage	Latency (ns)
Request	(1) FPGA HT IP core	70
	(2) host HT controller	32
SDRAM	(1) access and data fetch	51
	(1) host builds response packet	12
Response	(2) host HT controller	30
	(3) FPGA HT IP core	110
	Total Latency	305