A Dynamic Dual Fixed-Point Arithmetic Architecture for FPGAs
Figure 11
Performance bound curves at the theoretically maximum possible reconfiguration data rate speeds for Virtex II Pro MicroBlaze (a) and Virtex 4 PowerPC405 (b). Here, 0% cannot be represented in our logarithmic scale, thus it was included as the leftmost point in the graph. The original speed measurement (square red) was taken using running hardware systems described in Section 5. The round (black), plus (blue), and triangle (pink) curves were estimated scaling the results from the original speed measurement.
