A Dynamic Dual Fixed-Point Arithmetic Architecture for FPGAs
Figure 9
Performance results for a single DDFX core versus reconfiguration frequency for Virtex II Pro MicroBlaze (a) and Virtex 4 PowerPC405 (b). Here, 0% can not be represented in our logarithmic scale, thus it was included as the leftmost point in the graph. These measurements were taken using running hardware systems described in Section 5.
