A Dynamic Dual Fixed-Point Arithmetic Architecture for FPGAs

Table 3

Implementation results for Virtex II Pro (XC2VP30) using ISE 9.2.4i with default settings.

	FX (32_24)	DDFX (32_24_4)	SFPU
Addition
Equiv. gates	1158	3514	11388
Max. freq.	≈163 MHz	≈204 MHz	≈197 MHz
Multiplication
Equiv. gates	17802	19820	20395
Max. freq.	≈178 MHz	≈179 MHz	≈168 MHz